This invention relates generally to field programmable gate array (“FPGA”) integrated circuit devices, such as programmable logic devices (“PLDs”), and other integrated circuits of that general type (all generically referred to for convenience as PLDs). More particularly, the invention relates to circuitry for precision signal amplitude detection without pattern dependencies for inclusion on PLDs.
PLDs are intended to be relatively general-purpose devices. A PLD can be programmed (i.e., configured) and/or otherwise controlled to meet any need within the range of needs that the PLD is designed to support. A PLD may be equipped with high-speed serial data communication circuitry, whereby the PLD can transmit serial data to and/or receive serial data from circuitry that is external to the PLD. In that case, it is desirable for the high-speed serial data communication circuitry of the PLD to be able to support various communication protocols that various users of the PLD product may wish to employ.
In the case of high-speed serial data transmitter circuitry on a PLD, one of the tasks that such circuitry typically needs to perform is serialization of data from the parallel form in which it is typically generated and/or handled in the core logic circuitry of the PLD to the serial form in which the transmitter transmits it off the PLD.
In the case of high-speed serial data receiver circuitry on a PLD, one of the tasks that such circuitry typically needs to perform is deserialization of data from the serial form in which it is typically received from a source external to the PLD to the parallel form in which the receiver circuitry preferably hands the data off to other circuitry of the PLD (e.g., the core logic circuitry of the PLD). As such, many PLDs include integrated high-speed serializer/deserializer circuitry.
High-speed differential serializer/deserializer applications typically require the ability to detect extremely small differential input amplitudes to indicate a valid level. For example, in some signaling standards, such as PCI Express, a circuit must be capable of detecting differential signal amplitudes as small as 165 mV (peak-to-peak) at very high speeds. It is extremely difficult to design an accurate signal detector for these small amplitudes without pattern dependencies at gigabit per second data rates.
Amplitude detection (or peak detection) is also used in many other applications other than differential signaling. For example, amplitude detection may be useful in envelope detection and for extracting the absolute value of a signal. However, a transitioning differential signal has dips or levels lower than the signal's DC value. The dips are pattern-dependent, since more dips are seen in signals with higher transition densities. This may result in rectified voltage levels which are also pattern-dependent. This pattern-dependency is highly undesirable, especially in high-speed differential signaling standards, where accurately detecting very small voltage amplitudes is crucial.
Accordingly, it is desirable to provide precision circuitry for amplitude detection without pattern dependencies. The detection circuitry may be integrated with high-speed serial data communication circuitry of a PLD. For example, the amplitude detection circuitry may be integrated on one or more input pins of a PLD. The high-speed serial data communication circuitry and the precision amplitude detection circuitry may operate in the Gbps (gigabit per second) range.